An analog-to-digital converter (ADC) is an interface between the analog domain and the digital domain. Several different ADC architectures exist. The time-interleaved (TI) ADC architecture can be used in order to achieve a relatively high sampling rate. A number M of slower sub ADCs are configured to operate on the same input signal, but on different samples. Each sub ADC is configured to operate on every Mth sample. Thereby, an overall increase in sampling rate with a factor M is achieved for the TI ADC compared with an individual sub ADC.
A problem with TI ADCs is that mismatch between individual sub ADCs, e.g. gain and dc offset mismatch, causes distortion in the output signal of the TI ADC, typically showing up as spurious tones, visible as peaks in a signal spectrum.
One way to reduce such unwanted peaks is to add additional, redundant, sub ADCs to the TI ADC. Thereby, there are several sub ADCs available for each new sample. Hence, the order in which the sub ADCs are operated does not have to be periodic, but can be scrambled, e.g. in a random or pseudo random way. In this way, distortion peaks can be reduced, and the errors are smeared out over a larger frequency range. In this disclosure, we refer to such a TI ADC as a redundant TI ADC. An example of such a redundant TI ADC is given in K. El-Sankary, A. Assi and M. Sawan, “New sampling method to improve the SFDR of time-interleaved ADCs,” Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, pp. I-833-1-836 vol.1.